1. Field of the Invention
The present invention relates to verification of large-scale integrated circuits under design.
2. Description of the Related Art
At the design stage of large-scale integration (LSI), simulation is used to verify whether a circuit will operate as desired. For simulations implemented by software, the larger the scale of the circuit, the more time is required for the simulation. Therefore, techniques involving the mounting of an LSI circuit under design on a field programmable gate array (FPGA) or other such hardware are used to execute the simulation.
Japanese Patent Application Laid-Open Publication No. 2000-215226 discloses a technology involving the use of a software simulator and a hardware simulator to perform circuit verification. Specifically, logical information is read from a recording medium, where a portion of the logical information that is determinate to a configuration level is verified by the hardware simulator, while other portions are verified by the software simulator.
Although simulation employing an FPGA is faster than simulation via software, there are limitations to the scale of the circuit that can be simulated. In particular, when the operation of a system having multiprocessor architecture for increased processing speed is verified, a problem arises in that the scale of the circuit integrating the multiple cores becomes too large to fully mount on the FPGA.
For example, in a system having multiprocessor architecture, identical central processing units (CPU) operate communicating through a bus. Conventionally, when a system having n CPUs connected is to be simulated, the circuit volume becomes n times as great. Thus, a problem arises in that simulations of larger scale circuits become dependent upon software, thereby inviting prolonged design periods.
On the other hand, when operation is confirmed for portions other than actual processors, the use of pseudo processors having reduced circuit volumes may prevent such problems concerning LSI circuits such as systems having multiprocessor architecture.
However, a problem of reduced design accuracy arises as the simulated operation may not coincide with the actual operation causing omissions to occur. Further, as the pseudo processors have to be created, which requires time and labor, in the end, the problem of a prolonged design period arises.